1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming shallow buried contact junctions in the fabrication of integrated circuits.
2. Description of the Prior Art
A typical buried contact process flow is to deposit a doped layer of polysilicon over and on the planned buried contact regions, which may be source/drain regions. The structure is heated and the source/drain regions are doped by outdiffusion of dopants from the doped polysilicon layer into the silicon substrate. The doped polysilicon layer is allowed to remain on the source/drain regions as their contacts. This is called the buried contact process.
Because of the high diffusivity of the polysilicon dopant, it is difficult to control junction depth. A number of patents have addressed this and other problems involving forming source/drain regions. U.S. Pat. No. 5,049,514 to Mori shows a process of doping polysilicon, forming an opening to the substrate, forming a metal silicide layer within the opening, ion implanting, and annealing to form the source/drain region. U.S. Pat. No. 5,030,584 to H. Nakata describes a process involving outdiffusion to form source/drain regions and to leave the contact and source of dopants for the source/drain regions in place. While this patent's invention has the advantage of self alignment of the contact to the source/drain, it does not have the desired tailoring of the source/drain regions to the optimum conditions for the under one micron era. Patent disclosure Ser. No. 07/941229 to J. Y. Lee filed on Sept. 9, 1992 uses two layers of polysilicon to form a buried contact region in the substrate, However, only poly 2 actually touches the substrate.